This invention is related generally to reduced power logic and more specifically to reduced power logic having full voltage output swing and operating with recycled energy.
In related application, xe2x80x9cLOW POWER DYNAMIC LOGIC GATE WITH FULL VOLTAGE SWING OPERATIONxe2x80x9d a full voltage swing logic gate is disclosed. The full swing logic gate is configured to be precharged during a first phase of an input clock and to evaluate a logic function of its inputs on a second phase of the input clock. FIG. 1 shows a precharge path 10 under the control of a control circuit 12 by which the output node 20 of the circuit is precharged during a first phase of the clock 16 and a logic path 14 by which the logic function of the input 22 is evaluated during a second phase of the clock 16.
FIG. 2 shows an embodiment of the invention, an inverter 24, disclosed in the above-mentioned related application. The inverter 24 uses n-channel transistor 26 as the discharge path 14 and a p-channel transistor 28 as the precharge path 10. The control circuit includes a diode-connected p-channel transistor 30 and a diode-connected n-channel transistor 32, connected in parallel, between the drain and gate of the precharge transistor 28.
In operation, according to FIG. 3, when the signal on the clock input 16 is high, the p-channel precharge transistor 28 charges the output node 20 to a voltage substantially close to the high voltage of clock signal (VHxe2x88x92Vxcex4), where VH is the high voltage of the clock signal and Vxcex4 is the drop across the transistor channel while in the constant-current region. Vxcex4 can be made sufficiently small by adjusting the channel width-length ratio (W/L). When the signal on the clock input 16 is low, the n-channel logic path 14 evaluates the logic input 22 and depending on whether the input 22 is high or low, may discharge the output node 20 to a voltage substantially close to the low voltage VL of the clock signal (VL+Vxcex4). The result is that the output node has swing that is substantially close to a full logic swing, the output voltage being substantially close to either the high or low of the clock signal. As FIG. 3 shows, there is no Vt drop at the output 20.
One disadvantage of this circuit is that the circuit is precharged on one phase of the clock signal and evaluates the logic input or inputs on only one phase of the clock signal, thus taking, in effect, a full clock cycle to compute a logic function. Taking a full clock cycle to perform a logic function may be disadvantageous in some cases where speed of the computation is an issue. Therefore, there is a need to have a faster logic circuit that retains the benefits of low-power full swing operation.
The present invention is directed towards the above need. A logic circuit, in accordance with one embodiment of the present invention, includes a logic path, a pre-discharge path and a control circuit. The logic path is connected between a clock input and an output node and includes one or more transistors configured to evaluate a logic function of a data signal on at least one input during an evaluation phase. The pre-discharge path is connected between the clock input and the output node and includes an n-channel transistor having a gate and a channel definable between a source and drain region of the transistor, the channel being connected between the output node and the clock input. The control circuit has an output connected to the gate of the pre-discharge path transistor and is configured to maintain a source-to-gate voltage on the pre-discharge path transistor such that, independent of the states of the data input and the output node, the channel of the pre-discharge transistor provides a conductive path between the output node and the clock input during a pre-discharge phase.
Another logic circuit in accordance with the present invention includes a precharge path, first and second control circuits, first and second logic paths and a pre-discharge path. The precharge path is connected between a clock input and a first output node and includes a p-channel transistor for charging the first output node to a first voltage (high) on the clock input. The first control circuit is configured to provide a gate voltage to the p-channel transistor so that the p-channel transistor conducts while the first voltage is on the clock input. The first logic path is connected between the clock input and the first output node and has a first data input. The first logic path is configured to evaluate a logic function of the first data input during the second (low) voltage of the clock input. The pre-discharge path is connected between the clock input and a second output node and includes an n-channel transistor for pre-discharging the second output node to the second voltage on the clock input. The second control circuit is configured to provide a gate voltage to the n-channel transistor so that the n-channel transistor conducts while the second voltage is on the clock input. The second logic path is connected between the clock input and the second output node and has second data input. The second logic path is configured to evaluate a logic function of the second data input during the first (high) voltage of the clock input. The logic circuit provides logic evaluations when either the first or second voltage is present on the clock input.
An advantage of the present invention is that logic evaluations can be made on each phase of the waveform on the clock input, thereby making logic evaluations available to other circuit more quickly than if logic evaluations were made on only one phase of the clock waveform.